The present invention relates to a method for fabricating DRAM cells.
There is great pressure to scale dynamic ram cells to ever higher densities. However, as the conventional (single transistor single capacitor) DRAM cell is scaled to higher densities (e.g. beyond 64K), it is important that the storage capacitance of the cell not be scaled. That is, if the charge in the storage capacitor in the DRAM cell becomes less than around 250 Femtocoulombs, the exposure to alpha particle-induced errors becomes disastrously larger. Since substantial capacitative loading from the access lines on the chip is inevitable, the number of electrons stored in the cell is already near the practical limits permitted by sense amplifier operation. Only incremental improvement in this respect can be anticipated. Therefore, the number of electrons stored in a DRAM cell must be relatively high. However, unless operating voltages are to be increased (which seems extremely unlikly), this unscalable limitation on the amount of stored charge imposes an unscalable limitation on the capacitance of the storage gate. If the storage capacitance is fixed and unscalable, then the only parameter which can be varied to achieve physically smaller storage gates is the specific capacitance of the storage gate capacitor. Unless the physical size of the storage gate can be reduced while maintaining the same capacitance level, scaling of the conventional DRAM cell to one megabit and beyond will certainly be very difficult, and maybe completely uneconomical.
Thus it is an object of the present invention to provide a DRAM cell having a very high specific capacitance on the storage gate.
It is a further object of the present invention to provide a DRAM cell having a storage gate with a capacitance of at least 50 femtofarads at a voltage of five volts, wherein the storage gate has an area of less than 12 square microns.
One approach which has been proposed to provide higher specific capacitance on the storage gate on DRAMS is to provide an upper storage capacitor for the DRAM cell. That is, over the storage gate (e.g. in first poly) is provided an upper conductive layer, which defines at least part of the storage capacitance. This approach can be performed using a second poly (polycide) or a third poly (polycide) upper plate for the storage capacitor. In either case, it is preferable to also be able to use the second (or third) poly level for transistors in the peripheral circuits, and therefore a regrown gate oxide is preferably used for such transistors. However, the formation of such a regrown gate oxide is likly to cause uncontrolled increase in the thickness of the dielectric layer over the first poly storage gate, in prior art methods.
In prior art methods of forming a dielectric over a poly level, the equivalent dielectric thickness of the layer over the first poly storage gate may be rather high, due to this thickness increase.
Thus it is an object of the present invention to provide a DRAM cell having a very thin dielectric over a polysilicon storage capacitor Gottem plate.
The asperity of polysilicon presents a significant difficulty. In particular, increased doping of the polysilicon tends to produce more asperity, and increased thickness of the polysilicon also tends to produce more esperity. A recent paper has indicated that many asperities are generated during the thermal oxidation process, and are not found in the topography of the as-doped poly. See Shu et al. "Polysilicon/silcon dioxide Interface Microtexture and Dielectric Breakdown," Journal of the Electrochemical Society, Volume 129, Page 1282 (1982), which is hereby incorporated by reference. The as-doped poly has "hard spots" which are resistance to oxidation. These hard spots will generate inclusions and protuberances during the oxidation process.
Thus it is a further object of the present invention to provide a method for forming a good dielectric over polysilicon without requiring thermal oxide growth on the polysilicon.
A dynamic RAM cell having capacitative storage in a poly-to-poly capacitor is disclosed in M. Koyanagi et al. "Novel High Density, Stacked Capacitor MOS RAM," Jap. Jour. Appl. Phys. Pages 18,35 (1978), which is hereby incorporated by reference. A more recent publication which also shows an upper storage capacitor in a DRAM structure is found in K Ohta et al, "Quadruple Self-Aligned Stacked High-Capacitance RAM Using Ta.sub.2 O.sub.5 High-Density VLSI Dynamic Memory," IEEE Transactions on Electron Devices, Volume ED 29, Page 368 (1982) which is hereby incorporated by reference.
In addition, the use of composite dielectrics at some point in a DRAM cell is believed to be generally known. However, no known DRAM cell uses a composite dielectric over polysilicon. In particular, no DRAM cell uses a composite dielectric over silicon for a storage capacitor.
The multi-dielectric stack used in the present invention is much like the multi-dielectric stacks also used in the prior art of multi-dielectric memory cells. However, in the present invention, the semiconductor on both sides of the stack is heavily doped. Where light doping levels are used, trapped charge within the dielectric stack can be sensed, but heavy doping levels the operation of the device is quite insensitive to trapped charge, as is desirable in DRAM cells.
A difficulty of pure nitride films for capacitor to capacitor dielectric is that the nitride readily accepts trapped charge. This means that the threshold voltage across the dielectric stack will shift with the operating history of the array, and eventually the same write voltage on the common electrode of a number of capacitors will produce widely varying voltages on the respective second electrodes of capacitors, so that in effect the set of capacitors will come to have apparently widely varying capacitances.
This sensitivity to the threshold voltage is minimized by having a high doping density in both electrodes of the capacitor.
In the art of analog circuits, a common technique for producing precision poly to poly capacitors is to lightly dope the first level of poly (bottom plate) to 100 ohms/sq, so a uniform and reasonably thin dielectric can be grown at the same time the gate oxide is regrown. Second level poly is then used as the top plate. However, this means that the lower poly level cannot be used for interconnects.
The present invention teaches a technique for fabricating poly to poly capacitors with a high capacitance/unit area, e.g. 2.4 0.8 pF/mil.sup.2. The technique utilizes a composite oxide/nitride/oxide dielectric whose thickness is controlled independently of the regrown gate oxide, without the requirement of an extra mask. The composite dielectric has very good integrity, typical breakdown for a 100 .ANG. equivalent layer is around 10. In some of the test experiments the oxide and nitride layers were formed by LPCVD. These have exhibited high uniformity, better than 0.005%/mil or 3% across a 3" slice. A further advantage of using an LPCVD dielectric is that poly 1 can be doped to about 15 ohms per square since it is no longer necessary to thermally grow a uniform oxide. This gives the designer the flexibility of using both heavily doped 1st poly and silicided 2nd poly for interconnect.
Thus it is an object of the present invention of to provide a method for fabricating capacitors having high specific capacitance for integrated circuits.
It is a further object of the present invention to provide a method for fabricating capacitors having high specific capacitance in a standard MOS process.
Forming a precision capacitor over a first poly level is particularly difficult, since the surface of the first poly level will normally not be as smooth as that of a monocrystalline polished semiconductor surface, that is, the surface of even good poly will normally have a certain amount of unevenness. This unevenness can significantly affect the thickness of an oxide which is formed over the poly. It not only leads to uncertainty in the average specific capacitance, but also can cause formation of areas where an oxide grown over poly is locally thin.
Thus it is a further object of the present invention to provide a method for reliable fabrication of uniform dielectrics over a polysilicon level. The roughness of the polysilicon surface means that pinholing through a dielectric grown over first poly can occur. This problem becomes particularly serious if the dielectric is a thin one, as is required for high specific capacitance. This is a major concern in large analog integrated circuits, since the large total area devoted to capacitors means that even a small density of capacitor pinholes can cause drastic yield degradation.
Thus it is a further object of the present invention to provide a thin poly-to-poly dielectric having a very low density of pinholes.
In double poly processes, a regrown gate oxide is normally used to form transistors having second poly gates. That is, after the first poly level has been completely formed, the areas where transistors and second poly are to be formed are cleared down to silicon, and the gate oxides for second poly transistors are grown from scratch. However, the oxidizing conditions which permit growth of the second gate oxide also promote growth of oxide over the first poly level. Moreover, oxide normally grows faster on doped poly than on crystalline silicon under the same conditions, so that a thicker oxide will be formed over the first poly level. Where the oxide has already been formed over the first poly level before growth of the second gate oxide, as is typical, the oxide thickness over the first poly will be increased by the oxidizing conditions.
The second gate oxide will of course normally be grown to a precisely controlled thickness, but the simultaneous thickness increase of the oxide over the first poly may not be adequately controlled. The chief reason for this is because of doping uncertaintly. The oxidizing rate is a function of the polysilicon doping level, and the doping level itself cannot be precisely controlled in highly conductive POCl.sub.3 -doped polysilicon. Even if the polysilicon doping is performed by ion implantation, the average doping level in polysilicon will still be sensitive to the thickness of the polysilicon level deposited, which is also normally not a parameter which can be precisely controlled.
Thus it is an object of the present invention to provide a method for growth of a second gate oxide without any uncontrolled change in the thickness of an existing oxide over a first polysilicon level.
Thus it is an object of the present invention to provide a method for growth of a second gate oxide without simultaneously growing a thick oxide over first poly.
It is a further object of the present invention to provide a method for growing a second gate oxide without increasing the thickness of a dielectric over a first poly level.
A further problem with formation of capacitors is uniformity of the specific capacitance across the wafer. This problem is most acute in data conversion circuits where nonuniformity of capacitors can sacrifice several bits of accuracy. If integrated data conversion circuits are to have performance competitive with custom-trimmed hybrid circuits, uniform specific capacitance is a must. This is also a problem with switched-capacitor filtering, where nonuniformity can substantially degrade filter characteristics.
Thus it is a further object of the present invention to provide a method for forming poly-to-poly capacitors with highly uniform specific capacitance across the wafer.
In the present invention a composite oxide/nitride/oxide dielectric is used over the first poly level, instead of the thermal oxide taught by the prior art. This means that very thin dielectrics can be used over first poly which have very high dielectric integrity (low level of pinholes) and very high dielectric strength (breakdown voltage). Moreover, the dielectrics formed by the present invention are virtually unaffected by the normal second gate oxide growth cycle, so that the problem of uncontrolled thickness increase vanishes.
A dynamic RAM cell comprising:
a silicon substrate;
a plurality of bit lines;
a plurality of storage capacitors, each comprising bottom and upper plates separated by a composite dielectric, said composite dielectric comprising both oxide and nitride, said bottom plate being polycrystalline and comprising silicon;
a plurality of transfer gates, each said transfer gate being positioned to selectively connect a respective first one of said storage capacitor plates to a respective one of said bit lines; and
means for connecting a constant voltage to the respective other one of said storage capacitor plates.
According to the present invention there is provided:
A method for fabricating DRAM cells comprising the steps of:
providing a silicon substrate;
defining moat regions within said silicon substrate;
defining a plurality of storage capacitor bottom plates, said bottom plates being polycrystalline and comprising silicon;
forming a poly-to-poly capacitor dielectric over said bottom plates, comprising the steps of
depositing a first level of oxide over said bottom plates, and
depositing a layer of nitride over said first level of oxide,
exposing said substrate to an oxidizing atmosphere, whereby regrown gate oxides are formed on exposed portions of said substrate and said nitride layer is only slightly oxidized;
forming a plurality of conductive elongated regions over said regrown gate oxides, and simultaneously forming capacitor top plates over said storage gates.